In recent years, in association with increase in an integration degree of LSIs, a scale of a circuit on which the LSIs are mounted has been becoming increasingly larger. The HDL is employed for a designing method in association with the tendency for larger scale integration. Because of the tendency, now logic circuits are designed by a plurality of designers each responsible for each block and by means of combining the blocks into one circuit, analyzing a clock system of each block.
When integrating a plurality of blocks into one circuit, if a clock is supplied to a block designed by one person from a block designed by another person and the clock is, for instance, a gated clock, a malfunction may occur in the block designed by the person due to generation of a hazard or for other reasons. In the case as described above, a designer of the block from which a clock is supplied intentionally notifies, in anticipation of the possibility of troubles such as generation of a hazard, a designer of the block to which the clock is supplied of the possibility.
However, if the designer of the block from which the clock is supplied does not notify the designer of the block to which the clock is supplied of the possibility of generation of a hazard or other trouble, or the former designer cannot anticipate the possibility, a trouble may be generated due to a hazard or for other reasons when integrating blocks For this reason, because of inadequate communication between designers or due to shortage of data, a vast quantity of time is required to analyze a cause for a trouble generated when combining blocks, which in return disadvantageously lowers the work efficiency. Especially when an unknown macro or a macro based on unclear specifications is incorporated into a system, and when old resources such as a portion of a net list used previously is used, analysis of the trouble is extremely difficult.